Due to the large number of components in state of the art electronic circuits, most of their design and production is computer implemented. Various operations are performed during design of the electronic circuit, for example, timing analysis for validating timing performance of an electronic design or different types of optimizations based on the electronic circuit. Performing these operations for large electronic circuits can take significant time. Furthermore, the analysis performed for these operations needs to be repeated multiple times for the same electronic design for various combinations of modes and corners. Semiconductor device parameters can vary with conditions such as fabrication process, operating temperature, and power supply voltage. A circuit fabricated using these processes may run slower or faster than specified due to variations in operating conditions or may even fail to function. Therefore above analysis is performed for various operating conditions to make sure that the circuit performs as specified under these conditions. Such operating conditions for a circuit are modeled using corners that comprise a set of libraries characterized for process, voltage, and temperature variations.
The analysis of a circuit is also repeated for different operating modes including, normal operating mode, test mode, scan mode, reset mode, and so on. For example, an electronic circuit used in a computer operates in a stand-by mode when the computer is in a stand-by mode. Similarly, during testing phase, a circuit may be operated in a test mode. A mode is modeled using a unique set of clocks, input voltages, and timing constraints in similar operating conditions.
For performing analysis during implementation and sign-off of a circuit, designers have to verify a large number of modes and corners. Each circuit design may have several modes and several corners. Typically each mode is verified for each corner conditions. A combination of a mode for a given corner is referred to as a scenario. The total number of scenarios for which the design needs to be verified is the product of the number of modes and number of corners. Since the number of scenarios for which a circuit design needs to be analyzed can be very high, the physical memory required for accommodating the design in memory and the run time for performing analysis can become impractical. Therefore, electronic circuit design tools attempt to reduce the number of scenarios they analyze in order to perform the analysis using reasonable amount of resources.
Conventional methods for reducing the large number of scenarios either do not provide significant improvements in the memory or run time requirements or do so at the cost of reducing the quality of results. For example, a system may ignore a large number of scenarios during analysis. In this situation, the final analysis may not satisfy requirements imposed by the scenarios that were ignored. This may be realized very late during the design or fabrication process and significant portions of the design process may have to be repeated. This results in significant delays and costs of the design and manufacture process.